Going to scale! Semiconductor production line makes high-quality superconducting quantum bits for the first time

As superconducting quantum bit platforms are moving towards the fabrication of increasingly larger and more mature scale practical quantum computers, the limitation of quantum bit inhomogeneity due to the lack of process control becomes more evident.

Recently, a team from the Belgian Microelectronics Research Center (IMEC) demonstrated a fully CMOS (Complementary Metal Oxide Semiconductor) compatible method for quantum bit fabrication [1] and showed results for overlapping Josephson junction devices with long coherence and relaxation times (100+ µs). This fabrication process heralds an important milestone toward a 300 mm CMOS process that can fabricate highly coherent superconducting quantum bits and has the potential to drive the scale-up of superconducting device architectures.

01Conventional superconducting quantum bit process is not compatible with CMOS

One of the promising technologies in the quantum circuit model of computing is the use of superconducting circuits, of which quantum bits are an integral part, says IMEC senior researcher Anton Potočnik: "The energy state of superconducting quantum bits is relatively easy to control, and over the years researchers have been able to couple more and more quantum bits together. This is one of the pillars of quantum computing, and research groups around the world have demonstrated that superconducting quantum bits have long coherence times (up to a few hundred microseconds), sufficiently high gate fidelity, and they are two important benchmarks for quantum computing."

So far, these encouraging results have only been obtained on a laboratory scale: using "double-angle evaporation" and "lift-off techniques) to fabricate the most critical component, the Josephson junction. "A superconducting quantum bit is essentially a nonlinear LC resonator circuit containing a nonlinear inductor (L) and a capacitor (C)," explains Anton Potočnik. "The Josephson junction acts as a nonlinear, non-dissipative inductor, which allows us to manipulate quantum bit energy states to represent, for example, the superposition of |0⟩ and |1⟩. To minimize any energy loss, i.e., to maximize the coherence time, the various interfaces contained in the structures that make up the junction and the capacitor must be as clean as possible. The presence of even a single atomic defect at one of these interfaces can result in the loss of energy from the quantum bits. This is why double-angle evaporation and stripping are the preferred fabrication techniques: they can provide these extremely clean interfaces."

But these fabrication techniques have a serious drawback: they are difficult to upgrade further to larger numbers of quantum bits. The variability of the Josephson energy of the evaporation junction hinders large-scale implementation; in addition, the fabrication techniques limit the choice of superconducting materials (which are considered incompatible with advanced CMOS fabrication), thus limiting the potential for quantum bit improvements.

02Alternative: CMOS-compatible fabrication techniques

Dr. Jeroen Verjauw, a researcher at IMEC, said, "Our team at IMEC has explored alternative methods for fabricating superconducting circuits. Our focus is to create 'overlapping Josephson junctions' using only CMOS-compatible materials and techniques, as this can take advantage of the reliability, repeatability offered by state-of-the-art CMOS processing steps to control quantum bit degeneracy and facilitate scale-up."

The overlapping junction has two electrodes (bottom: BE and top: TE), separated by a thin insulating layer. The electrodes are defined in two patterning cycles with a vacuum interruption in between. This interruption introduces an uncontrolled growth of the native metal oxide, which must be removed in the "Ar-milling" step. "However, the Ar-milling step is known to be very critical: it has been previously reported to introduce unnecessary energy losses." Jeroen Verjauw added [2].

(a) Cross-sectional view of Josephson junction. The overlap between the bottom electrode (BE) and the top electrode (TE) defines the Josephson junction and the (parasitic) stray junction; (b) wet etched BE junction cross section. ar milling induced amorphous silicon layer is visible below the TE layer (green interface in a); (c) quantum bit energy relaxation measurements and (d) average gate fidelity and average error per gate.

In response to the experimental results, Tsvetan Ivanov, another researcher, said, "We have demonstrated in the laboratory that the coherence time of superconducting quantum bits exceeds 100µs with an average single quantum bit gate fidelity of 99.94%. These results are comparable to state-of-the-art devices, however, they are the first to be obtained using CMOS-compatible fabrication techniques. These breakthrough results can be achieved by improving known overlapping junction fabrication processes: improvements include process optimization to reduce the number of process steps and interfaces (and therefore the risk of energy loss), improved Ar milling steps, and the exclusive use of aluminum (Al) to fabricate the electrodes."

03Device size will be reduced for application on large area wafers

So far, however, the experiments described in this paper have only been implemented on thin insulating layers in a laboratory environment.

Tsvetan Ivanov said, "The proposed fabrication method heralds an important milestone toward a high-quality superconducting quantum bit manufacturable 300mm CMOS process. Soon, we will transfer the fabrication of these superconducting circuits to IMEC's 300mm wafer fab: we are eager to verify if high coherence times can be reproduced on larger wafer substrates."

Similarly, Jeroen Verjauw said, "We have also designed tests in order to investigate the source of energy loss. Preliminary results show that the loss occurs mainly on the outer surface of the structure, rather than at critical junctions. This is encouraging, as it leaves more room for optimization. Finally, our fabrication method provides a way to fabricate repeatable quantum bits on large area wafers."

However, there are other obstacles on the road to a practical superconducting quantum computer. anton Potočnik concludes, "For example, superconducting quantum bits are still relatively large (mm scale) compared to semiconductor spin quantum bits (nm scale). We are working on ways to further shrink the device, and a lot of work is going on in terms of algorithms. The quantum bits we make today are not ideal, so there is a huge effort on the theoretical side to develop algorithms that are more resilient to losses and errors, and quantum error correction protocols. Most importantly, well-calibrated instruments need to be connected to an increasing number of superconducting quantum bits, control them and read out meaningful results."

04Summing up and looking ahead: progress on the right track

In this experiment, IMEC's quantum computing team demonstrated a fully CMOS-compatible method for fabricating superconducting quantum bits.

Finally, Kristiaan De Greve, director of IMEC's quantum computing program, sees the results of the work of Anton, Tsvetan, Jeroen and others as an important milestone, overcoming a fundamental obstacle to superconducting quantum bit upgrading with the advantages of industrial control and accuracy - standard processing As future quantum processors may require thousands to millions of physical quantum bits, it is critical to overcome the limitations imposed by variability and low yields," Greve said. Therefore, IMEC is on the right track in understanding and benchmarking these limitations, and introducing new solutions is taking our semiconductor and superconductivity experience-based quantum computing to the right place."

Reference link：

[1] https://www.nature.com/articles/s41534-022-00600-9

[2]https://phys.org/news/2022-08-high-quality-superconducting-qubits-fabricated-cmos-compatible.html