Silicon spin qubits towards industrialization using FDSOI to realize linear silicon quantum dot arrays

Silicon spin qubits are one of the most promising avenues toward practical quantum computing. New research on room-temperature parametric testing procedures by a research team from France supports the powerful performance potential of silicon spin qubits and the opportunity to simplify their transition to manufacturing by leveraging well-characterized processes and materials from the semiconductor industry.

Researchers from French research institutes CEA-Leti, Grenoble-Alpes University, CNRS Institut Néel and CEA-Irig presented the paper " Characterization of FDSOI Quantum Dot Array Integration and Characterization" [1], they share a new three-step characterization chain for the fabrication of linear silicon quantum dots on fully depleted silicon-on-insulator (FDSOI) materials (QD) arrays .

The researchers say this is a "powerful step toward industrialization" for silicon spin qubits.

Quantum Dot Qubit Array Using FDSOI

Fully depleted silicon-on-insulator (FDSOI) is a planar process technology invented in 2000. Compared with other silicon technologies, FDSOI can achieve effective control of transistor current and flexible regulation of threshold voltage under the nano-node process. Therefore, at the beginning of the 21st century, European semiconductor research institutions and companies represented by Leti, Soitec, and STM began to invest. development of this technology.

The three-step characterization chain approach in this paper enables developers to detect and analyze problems at the earliest and easiest time points to maximize the effectiveness of high-temperature testing as part of a broader push to make silicon QD devices manufacturable. "This is a powerful step towards industrialization," said Dr. Maud Vinet, Director of the CEA-Leti Quantum Computing Program.

The initial wafer-level room temperature characterization step collects data in a few hours using a transistor-like test protocol, followed by a more time-consuming wafer-level QD characterization step at temperatures below 2K (-271.15°C) and at temperatures below 100mK Chip-scale qubit manipulation steps (may take several days per device).

The research team used this process to evaluate several considerations related to the production of integrated QD arrays and make recommendations to address them:

1) Linear arrays using floating gate quantum dots work in a similar way to single gate standard transistors. The researchers found that the inner gates in these arrays provided consistently advanced performance in threshold voltage (Vth) and subthreshold slope (SS), but the outer gates exhibited more variability. The paper concludes by suggesting that these edge-effect properties can be addressed by using the outer gate as an access gate rather than confinement quantum dots, as this can be caused by factors such as random dopant fluctuations.

2) Furthermore, the paper states that while the split-gate design of linear quantum dot arrays being explored offers several functional advantages, its successful implementation requires very tight coverage control for one specific lithography step to achieve good symmetry. , which is required for consistent performance.

3) The third proposal focuses on the problem of stray dots within the qubit layer, which is also the main source of lower yields in silicon QD arrays. Spurious spots can be detected during low temperature testing, but revealing the inter-gate defects causing them early in the characterization chain (eg, at a 300K test cycle) will greatly speed up the test cycle. While standard transistor parametric testing is not suitable for this task, the researchers developed a 300K (26.85°C) voltage sweep technique capable of monitoring the screening effect of inter-gate defects on exchange gate polarization.

A key advantage of the FDSOI material the team used, Vinet said, is that the back gate can be used to draw charge away from the interface. Back gates are typically fabricated using dopant implantation, which has the potential to introduce defects or parasitic dopants into the qubit layer. She adds that an alternative fabrication method using a TSV-like metal back-gate electrode would be one way to mitigate this shortcoming, while also enabling reverse biasing [2].

"These findings represent an important step toward addressing the broader challenges of silicon spin qubit integration that we discussed at last December's IEDM meeting," said Heimamu Niebojewski, principal device engineer at CEA-Leti. A very encouraging sign."

About CEA

The CEA (French Commission for Atomic and Alternative Energies) is a key player in development and innovation in four main areas: energy transition, digital transformation, future medical technologies, and defence and security. CEA plays a key role in transferring scientific knowledge and innovation from research to industry. Leti is CEA's technology research institute, established in 1967, a pioneer in micro-nano technology.

CEA-Leti addresses key challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, CEA-Leti's multidisciplinary team provides solid expertise utilizing world-class industrialized facilities.

Reference link:

[1] https://www.nanotech-now.com/news.cgi?story_id=57091#:~:text=In%20an%20invited%20paper%2C%20%E2%80%9CSpecificities%20of%20FDSOI% 20QD, arrays%20fabricated%20on%20fully%20depleted%20silicon-on-insulator%20%28FDSOI%29%20material.

[2] https://www.leti-cea.com/cea-tech/leti/english/Pages/What's-On/Press%20release/CEA-Partners-Industrialization-Quantum-FDSOI-Material.aspx