Finally come! IBM unveils technical details of 127-qubit chip
Last November, IBM Quantum announced the Eagle, a 127-qubit (127-Q) quantum processor based on the transmon superconducting qubit architecture. However, IBM did not release further details beyond the number of qubits. Now, the technical details about Eagle are finally here.
Recently, IBM Quantum benchmarked their 27-qubit Falcon processor, 65-qubit Hummingbird processor, and 127-qubit Eagle processor in the following 3 areas:
1. Number of qubits
2. Quantum volume
3. CLOPS (circuit layer operations per second)
In the five months since the Eagle's release, the IBM Quantum team has had the opportunity to analyze the Eagle's performance, compare it to that of previous processors such as the IBM Quantum Falcon, and incorporate lessons learned into further revisions middle. At the recent APS March conference, IBM presented an in-depth look at 127-qubit technology, a comparison between Eagle and Falcon, and benchmarks for the latest Eagle version.
127-qubit Eagle processor
Multilayer wiring and silicon vias
Like all of IBM's processors, Eagle relies on the architecture of superconducting transmon qubits. These qubits are either anharmonic oscillators, Josephson junctions (a quantum hardware element consisting of potential barriers placed between superconducting wires capable of creating the quantum effects required for functional qubits) or gaps in superconducting circuits as Non-linear inductance introduces anharmonicity.
IBM implemented a single-qubit gate using specially tuned microwave pulses, which introduced superposition and changed the phase of the qubit's quantum state. The two-qubit entanglement gate was achieved using tunable microwave pulses called cross resonance gates, which illuminate the control qubit at the transition frequency of the target qubit. Performing these microwave activation operations requires us to be able to transmit microwave signals with high fidelity and low crosstalk.
Eagle's core technology advancement is the use of IBM's third-generation signal transmission scheme. IBM's first-generation processors consisted of a layer of metal and a printed circuit board on a qubit wafer. While this scheme works for ring topology, where the qubits are arranged in a ring, it fails if there are any qubits in the center of the ring, because there is no way to transmit a microwave signal to them.
The second-generation packaging scheme uses two separate chips, each with a patterned layer of metal connected by superconducting bump bonds: a qubit wafer on top of an interposer wafer. This scheme brings microwave signals to the center of the qubit chip, the cornerstone of the Falcon and Hummingbird processors. However, it requires that all qubit control and readout lines be routed to the periphery of the chip and that the metal layers are not isolated from each other.
Comparison of three generations of chip packaging
As before, Eagle has a qubit wafer bump bonded to an interposer wafer. The difference is that IBM has now added multilayer wiring (MLW) to the interposer. They routed their control and readout signals in this extra layer, which is well isolated from the quantum device itself and can deliver signals deep inside the large chip.
The MLW layer consists of three metal layers, a patterned planarized dielectric between the layers, and short connections (called vias) connecting the metal layers. These energy levels allow the fabrication of transmission lines that are isolated from each other and completely isolated from quantum devices. They also added through-substrate vias to the qubit and interposer chips.
In qubit chips, this allows it to suppress the Box Model, which is a bit like a microwave version of glass that vibrates when you sing a specific pitch in it. It also allowed them to build grids of holes—dense walls of vias—between qubits and other sensitive microwave structures. If the distance between them is much less than one wavelength, these vias act like a Faraday cage, preventing capacitive crosstalk between circuit elements. In an interposer chip, these vias serve the same role, while also allowing microwave signals to travel up and down the MLW to anywhere inside the chip.
Reduce crosstalk
Classical crosstalk is an important source of error in superconducting quantum computers. IBM's chips have dense arrays of microwave wires and circuit elements that transmit and receive microwave energy. If any of these wires transmit energy to each other, the micro-tone tone they apply and intend to transmit to one qubit will transmit to the other.
However, for qubits coupled by a bus to allow a two-qubit gate, the desired quantum coupling from the bus may appear similar to the undesirable effects of classical crosstalk. The IBM team used a method called Hamiltonian tomography to estimate the effect sizes of the coupled busses and subtracted them from the total effect, leaving only the effects of classical crosstalk.
By understanding the extent of this classical crosstalk, for coupled qubits, it is even possible to use a second microwave "cancellation" tone on the target qubit during a two-qubit gate to cancel some of the effects of classical crosstalk. In other cases, it is impractical to compensate for this condition, and classical crosstalk increases the error rate of the processor - often requiring a newer version of the processor.
MLWs and TSVs (through silicon vias) provide Eagle with natural crosstalk shielding. As shown in the figure below, despite having more qubits and a more complex signaling scheme, the proportion of high crosstalk qubits in Eagle is much smaller than that in Falcon, and the worst-case crosstalk is much smaller.
These improvements are expected. In the Falcon, there are no TSVs, and the wire runs through the chip and can easily transfer energy to the qubits. For Eagle, each signal is surrounded by metal between the ground plane of the qubit chip and the ground plane on top of the MLW layer.
Classic amount of crosstalk between Falcon and Eagle. Note that this is a quantile plot. The median is x=0.
Meanwhile, for the qubits with the most crosstalk, the same qubits crosstalk the most on two different Eagle chips. This is exciting because it shows that the worst pairs of crosstalk are due to a design problem they haven't solved yet -- so this can be corrected in the next generation.
Although progress has been made in dealing with crosstalk, IBM still faces challenges. Eagle has 16,000 pairs of qubits. It takes a long time, about 11 days, to find those qubits with a crosstalk greater than 1%, and the crosstalk can be non-local, so there can be crosstalk between these pairs of qubits. They speed up the process by making crosstalk measurements on multiple qubits simultaneously. However, if they choose to run in parallel on two pairs with poor crosstalk, this measurement could be corrupted.
The IBM team is still learning how to acquire these datasets in a reasonable amount of time and collate the vast array of measurements to be able to better understand Eagle and prepare for larger devices in the future.
Performance comparison
While IBM uses quantum volume to measure synthetic "quality," there are now many finer metrics that characterize various aspects of device performance and guide the development of quantum processors, which they also track in Eagle.
Superconducting quantum processors face a variety of errors, including T1 (measuring relaxation from |1⟩ to |0⟩ states), Tϕ (measuring dephasing — randomization of qubit phases), and T2 (parallelization of T1 and Tϕ combination).
These errors are caused by imperfect control pulses, spurious inter-qubit coupling, imperfect qubit state measurements, and more. They are unavoidable, but the threshold theorem says that as long as we can reduce the hardware error rate below some constant threshold, we can build an error-correcting quantum computer. Therefore, the core mission of the IBM hardware team is to improve the coherence time and fidelity of the hardware, while scaling to processors large enough to be able to perform meaningful error-correcting computations.
IBM's initial measurements of the Eagle's T1 trailed the Falcon r5 processor's T1. Therefore, their two-qubit gate fidelity on Eagle is also lower than Falcon.
At the same time as Eagle was designing and building, they built a higher-coherence Falcon processor: the Falcon r8. This is a great example of the advantages of parallelism in scale and quality.
IBM applied these changes to Eagle r3. Now, the same coherence time as the Falcon r8, 400 microseconds, is achieved in Eagle. IBM expects improvements in the fidelity of two-qubit gates to follow. An ongoing focus of their research on Eagle is readout performance metrics. Two parameters control the readout: the coupling strength χ of the qubit to the readout resonator and the velocity κ of the photon leaving the resonator. There are trade-offs in choosing these parameters, so the most important design goals are to be able to choose these parameters accurately and to ensure that they are spread out across the device to a small extent.
Currently, Eagle is consistently and systematically lagging Falcon devices on χ as shown in the graph below (there is already a solution, with revisions planned in the future). In addition, Eagle's κ was found to be more widely distributed than Falcon, with the highest κ qubits higher and the lowest κ qubits lower in Falcon. IBM found that a mismatch between the frequency of the Purcell filter (a bandpass or notch filter that prevents qubit decay by emitting photons from its own readout resonator) and the readout resonator frequency may be at play -- IBM's hardware team is also working to improve in this area.
Comparison of χ and κ values for Falcon (Kolkata) and Eagle (Washington) chips
IBM considered the first round of testing of the new processor a great success. Reduced crosstalk, improved coherence time, normal readout, and other improvements while nearly doubling the size of the processor. Eagle also has improved measurement fidelity compared to the latest Falcon, but it's important to note that measurement times vary between processors.
Outlook
Eagle demonstrated the power of applying the principles of flexible development to research -- nearly doubling the size of the processor in IBM's first iteration of the device and making strides in improving quality thanks to reduced crosstalk.
Of course, IBM says they're only just beginning to tweak the processor's design. Expect to see further quality improvements for readout and frequency collisions in upcoming revisions.
At the same time, IBM is going all-in on quantum computing. They've started measuring coherence times in excess of 400 microseconds on the highest-performance processors -- and continue to push toward the lowest-error two-qubit gates.
IBM Quantum will still follow the roadmap to bring the 1121-qubit processor online by 2023, continue to deliver cutting-edge quantum research, and move forward in scale, quality and speed to deliver the best superconducting quantum processors. Preliminary testing of Eagle shows that IBM is on the right track.
Link:
https://research.ibm.com/blog/eagle-quantum-processor-performance
